The apparatus of the present invention generally relates to data processing systems and more particularly to data processing operations provided over a common input/output bus.
In a system having a plurality of devices coupled over a common bus an orderly system must be provided by which bidirectional transfer of information may be provided between such devices. This problem becomes more complicated when such devices include for example one or more data processors, one or more memory units, and various types of peripheral devices, such as magnetic tape storage devices, disk storage devices, card reading equipment and the like.
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those which have special paths between various devices. Such systems also may include a capability for either synchronous or asynchronous operation in combination with the bus type. Some of such systems, independent of the manner in which such devices are connected or operate, require the data processor's control of any such data transfer on the bus even though for example the transfer may be between devices other than the data processor. In addition such systems normally include various parity checking apparatus, priority schemes and interrupt strucures. One such structural scheme is shown in U.S. Pat. No. 3,866,181. Another is shown in U.S. Pat. No. 3,676,860. A data processing system utilizing a common bus is shown in U.S. Pat. No. 3,815,099. The manner in which addressing is provided in such systems as well as the manner in which for example any one of the devices may control the data transfers is dependent upon the immplementation of the system i.e. whether there is a common bus, whether the operation thereof is synchronous or asynchronous, etc. The system's response and throughput capability is greatly dependent on these various structures.
It is accordingly a primary object of the present invention to provide an improved data processing system having a plurality of devices, including the data processor, connected to a common bus.